1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a method for forming contact vias in integrated circuits.
2. Description of the Prior Art
As integrated circuit devices become more complex, greater numbers of interconnect levels are required to connect the various sections of the device. Generally contact vias are formed between interconnect levels to connect one level to another. When multiple layers of interconnect are used in this manner however, difficulties arise in forming upper interconnect levels and contact vias due to the uneven topographical features caused by the lower interconnect levels. Thus, the topography of interconnect layers affects the ease of manufacturing of the integrated circuit device.
The uneven topographical features of multiple interconnect levels are caused by forming the various interconnect layers above each other, resulting in the creation of hills and valleys on the surface of the device. Those skilled in the art will recognize it is difficult to get upper interconnect layers to maintain constant cross-sections when crossing over uneven topography. This leads to portions of the interconnect lines having a higher current density, leading to electromigration problems and related device failure mechanisms. These step coverage problems can result in voids and other defects in the interconnect signal lines themselves, and in the contact vias formed between interconnect lines.
Therefore, it would be desirable to provide a method for forming contact vias which are free of voids and other defects, and which result in a more planar topography. It is also desirable that such a method not significantly increase the complexity of the manufacturing process.